The invention relates to the plasma etching of a silicon wafer in the manufacture of integrated circuits.
As the density of circuit components contained within a semiconductor die has increased and the circuit components have decreased in size and are spaced closer together, it has become increasingly difficult to access selectively a particular region of the silicon wafer through the various layers that are typically superimposed on the surface of the silicon wafer without undesired interference with other active regions.
It is especially important to have a technology that can etch openings that have essentially vertical walls, most notably when the openings are to extend deeply into the surface layers. Additionally, to tolerate some misalignment in the masks used to define such openings, it is advantageous to provide protection to regions that need isolation but that inadvertently lie partially in the path of the projected opening. To this end it is sometimes the practice to surround such regions with a layer of material that resists etching by the process being used to form the openings.
Accordingly, a technology that provides the desired results will need an appropriate choice both in the materials used in the layers and the particular etching process used with the materials chosen.
Dry etching, such as plasma etching and reactive ion etching, has become the technology of choice in patterning various layers that are formed over a silicon wafer as it is processed to form therein high density integrated circuit devices. This is because it is a process that not only can be highly selective in the materials it etches, but also highly anisotropic. This makes possible etching with nearly vertical sidewalls.
Basically, in plasma etching as used in the manufacturing of silicon integrated devices, a silicon wafer on whose surface has been deposited various layers, is positioned on a first electrode in a chamber that also includes a second electrode spaced opposite the first. As a gaseous medium that consists of one or more gasses is flowed through the chamber, an r-f voltage, which may include components at different frequencies, is applied between the two electrodes to create a discharge that ionizes the gaseous medium and that forms a plasma that etches the wafer. By appropriate choice of the gasses of the gaseous medium and the parameters of the discharge, selective and anisotropic etching is achieved.
While elaborate theories have been developed to explain the plasma process, in practice most of such processes have been developed largely by experimentation involving trial and error of the relatively poor predictability of results otherwise.
Moreover, because of the number of variables involved and because most etching processes depend critically nor only on the particular materials to be etched bur also on the desired selectivity and anisotropy, such experimentation can be time consuming while success often depends on chance.
The reliability of a metal interconnect is most commonly described by a lifetime experiment on a set of lines to obtain the medium time to failure. The stress experiment involves stressing the lines at high current densities and at elevated temperatures. The failure criterion is typically an electrical open for non-barrier conductors or a predetermined increase in line resistance for barrier metalization.
The mean time to failure is dependent on the line geometry where this failure is directly proportional to the line width and the line thickness. Experimentally, it has been shown that the width dependence is a function of the ratio of the grain size d of the film and the width of the conductor w. As the ratio w/d decreases, the mean time to failure will increase due to the bamboo effect.
FIG. 1a shows a non-bamboo structure 10 in a wider line, that is a thin film or a fine line that is dominated by triple points 12.
FIG. 1b shows a bamboo-like grain structure 20 in a sub-micron line. As the grain size increases with respect to the line width, the interconnecting points of the triple points parallel to the length of the conductor decrease and even vanish. So the probability of voids accumulating along the grain boundaries is reduced, thus retarding the electro-migration process. The final grain structure 22 of the Al film is not only a function of the metal deposition conditions but is also strongly dependent on post-metalization annealing temperatures and the texture of the underlying surface.
U.S. Pat. No. 5,611,888 (Bosche et al.) shows contact hole plasma etch process.
U.S. Pat. No. 5,667,631. (Holland et al.) and U.S. Pat. No. 5,607,880 (Suzuki et al.) show dry etch processes.
U.S. Pat. No. 5,647,953 (Williams et al.) shows a post etch treatment to clean the etcher.
It is the primary objective of the present invention to eliminate bamboo profile on the inner surface of semiconductor contact holes.
Another objective of the present invention is to decrease the electrical resistivity for the contact holes within semiconductor devices.
Yet another objective of the present invention is to prevent the negative effects of the F-ion that is released during the GDP cleaning process.
Yet another objective of the present inventions is to increase the benefit of the protective polymer layer in the inside of the contact holes.
The present invention teaches a post etch treatment (PET) to perform the Gas Distribution Plate (GDP) polymer cleaning before the step of removing polymer in the contact holes. In a typical and previous sequence of post etch treatment (PET) procedures, the polymer in contact holes is remove first after which GDP polymer cleaning is performed. It is claimed that the polymer inside the contact holes avoids the formalion of the so-called bamboo rings within the contact holes. By having the polymer present within the contact holes while the GDP polymer cleaning is performed, no bamboo rings are formed. By removing the polymer within the contact holes after GDP polymer etching, the sidewalls of the contact holes are devoid of bamboo rings.